2. Layer Table
This chapter is a documentation of IHP layers definition which is valid in all technologies.
Tip
Only the layers described in the following table are allowed to be used in layout designs. Do not use layers exclusively reserved for internal usage.
Layer Name |
Purpose |
GDS Number |
GDS Datatype |
Description |
|---|---|---|---|---|
Activ |
drawing |
1 |
0 |
Defines active regions in substrate, where transistors, diodes and/or capacitors will be fabricated |
Activ |
pin |
1 |
2 |
Activ pin layer |
Activ |
mask |
1 |
20 |
added to Active: drawing at mask generation |
Activ |
filler |
1 |
22 |
Activ filler layer |
Activ |
nofill |
1 |
23 |
Activ filler exclusion layer |
Activ |
OPC |
1 |
26 |
Activ outer OPC definition layer |
Activ |
iOPC |
1 |
27 |
Activ inner OPC definition layer |
Activ |
noqrc |
1 |
28 |
No parasitics extraction |
BiWind |
drawing |
3 |
0 |
Defines active npn collector region |
BiWind |
OPC |
3 |
26 |
BiWindOPCdefinition layer |
GatPoly |
drawing |
5 |
0 |
Defines poly silicon gates and interconnect |
GatPoly |
pin |
5 |
2 |
GatPoly pin layer |
GatPoly |
filler |
5 |
22 |
GatPoly filler layer |
GatPoly |
nofill |
5 |
23 |
GatPoly filler exclusion layer |
GatPoly |
OPC |
5 |
26 |
GatPoly outer OPC definition layer |
GatPoly |
iOPC |
5 |
27 |
GatPoly inner OPC definition layer |
GatPoly |
noqrc |
5 |
28 |
No parasitics extraction |
Cont |
drawing |
6 |
0 |
Defines 1-st metal contacts to Activ, GatPoly |
Cont |
OPC |
6 |
26 |
Cont OPC definition layer |
nSD |
drawing |
7 |
0 |
Defines areas to receive N+ source/drain implant |
nSD |
block |
7 |
21 |
Defines areas which do not receive S/D implants |
Metal1 |
drawing |
8 |
0 |
Defines 1-st metal interconnect |
Metal1 |
pin |
8 |
2 |
Metal1 pin layer |
Metal1 |
mask |
8 |
20 |
added to Metal1: drawing at mask generation |
Metal1 |
filler |
8 |
22 |
Metal1 filler layer |
Metal1 |
nofill |
8 |
23 |
Metal1 filler exclusion layer |
Metal1 |
slit |
8 |
24 |
Metal1 slit definition layer |
Metal1 |
text |
8 |
25 |
Text layer for Metal1, used for LVS |
Metal1 |
OPC |
8 |
26 |
Metal1 OPC definition layer |
Metal1 |
noqrc |
8 |
28 |
No parasitics extraction |
Metal1 |
res |
8 |
29 |
Wire resistor |
Metal1 |
iprobe |
8 |
33 |
Current probe |
Metal1 |
diffprb |
8 |
34 |
Differential current probe |
Passiv |
drawing |
9 |
0 |
Defines regions where passivation coating is removed |
Passiv |
pin |
9 |
2 |
Passiv pin layer |
Passiv |
sbump |
9 |
36 |
Defines passivation openings for solder bump bonding |
Passiv |
pillar |
9 |
35 |
Defines passivation openings for copper pillar formation |
Passiv |
pdl |
9 |
40 |
Plasma dicing line |
Metal2 |
drawing |
10 |
0 |
Defines 2-nd metal interconnect |
Metal2 |
pin |
10 |
2 |
Metal2 pin layer |
Metal2 |
mask |
10 |
20 |
added to Metal2: drawing at mask generation |
Metal2 |
filler |
10 |
22 |
Metal2 filler layer |
Metal2 |
nofill |
10 |
23 |
Metal2 filler exclusion layer |
Metal2 |
slit |
10 |
24 |
Metal2 slit definition layer |
Metal2 |
text |
10 |
25 |
Text layer for Metal2, used for LVS |
Metal2 |
OPC |
10 |
26 |
Metal2 OPC definition layer |
Metal2 |
noqrc |
10 |
28 |
No parasitics extraction |
Metal2 |
res |
10 |
29 |
Wire resistor |
Metal2 |
iprobe |
10 |
33 |
Current probe |
Metal2 |
diffprb |
10 |
34 |
Differential Current probe |
BasPoly |
drawing |
13 |
0 |
Defines npn base poly region |
BasPoly |
pin |
13 |
2 |
BasPoly pin layer |
pSD |
drawing |
14 |
0 |
Defines areas to receive P+ source/drain implant |
NLDB |
drawing |
15 |
0 |
Reserved for internal LDMOS development |
DigiBnd |
drawing |
16 |
0 |
surrounds areas were digital DRC is valid |
Via1 |
drawing |
19 |
0 |
Defines 1-st metal to 2-nd metal contact |
BackMetal1 |
drawing |
20 |
0 |
Defines 1-st back-side metal interconnect |
BackMetal1 |
pin |
20 |
2 |
BackMetal1 pin layer |
BackMetal1 |
mask |
20 |
20 |
added to BackMetal1: drawing at mask generation |
BackMetal1 |
filler |
20 |
22 |
BackMetal1 filler layer |
BackMetal1 |
nofill |
20 |
23 |
BackMetal1 filler exclusion layer |
BackMetal1 |
slit |
20 |
24 |
BackMetal1 slit definition layer |
BackMetal1 |
text |
20 |
25 |
Text layer for BackMetal1, used for LVS |
BackMetal1 |
OPC |
20 |
26 |
BackMetal1 OPC definition layer |
BackMetal1 |
noqrc |
20 |
28 |
No parasitics extraction |
BackMetal1 |
res |
20 |
29 |
Wire resistor |
BackMetal1 |
iprobe |
20 |
33 |
Current probe |
BackMetal1 |
diffprb |
20 |
34 |
Differential Current probe |
BackPassiv |
drawing |
23 |
0 |
Defines regions where passivation coating is removed |
RES |
drawing |
24 |
0 |
Identifies resistor areas |
SRAM |
drawing |
25 |
0 |
Identifies memory areas |
TRANS |
drawing |
26 |
0 |
Identifies bipolar transistor areas |
IND |
drawing |
27 |
0 |
Identifies inductor areas |
IND |
pin |
27 |
2 |
IND pin layer |
IND |
text |
27 |
25 |
IND text layer |
SalBlock |
drawing |
28 |
0 |
Defines non salicided Activ and GatPoly, BasPoly areas |
Via2 |
drawing |
29 |
0 |
Defines 2-nd metal to 3-rd metal contact |
Metal3 |
drawing |
30 |
0 |
Defines 3-rd metal interconnect |
Metal3 |
pin |
30 |
2 |
Metal3 pin layer |
Metal3 |
mask |
30 |
20 |
added to Metal3: drawing at mask generation |
Metal3 |
filler |
30 |
22 |
Metal3 filler layer |
Metal3 |
nofill |
30 |
23 |
Metal3 filler exclusion layer |
Metal3 |
slit |
30 |
24 |
Metal3 slit definition layer |
Metal3 |
text |
30 |
25 |
Text layer for Metal3, used for LVS |
Metal3 |
OPC |
30 |
26 |
Metal3 OPC definition layer |
Metal3 |
noqrc |
30 |
28 |
No parasitics extraction |
Metal3 |
res |
30 |
29 |
Wire resistor |
Metal3 |
iprobe |
30 |
33 |
Current probe |
Metal3 |
diffprb |
30 |
34 |
Differential Current probe |
NWell |
drawing |
31 |
0 |
Defines the regions that receive P-Channel VT adjust, P-Channel Punch-Through and N-Well implants |
NWell |
pin |
31 |
2 |
NWell pin layer |
nBuLay |
drawing |
32 |
0 |
Defines bipolar sub collector and isolated NMOS devices |
nBuLay |
pin |
32 |
2 |
nBuLay pin layer |
nBuLay |
block |
32 |
21 |
Defines areas where non BuLay implantis allowed |
EmWind |
drawing |
33 |
0 |
Defines npn emitter window |
EmWind |
OPC |
33 |
26 |
EmWind OPC definition layer |
DeepCo |
drawing |
35 |
0 |
Defines deep collector regions |
MIM |
drawing |
36 |
0 |
Defines Metal-Insulator-Metal capacitor area |
EdgeSeal |
drawing |
39 |
0 |
EdgeSeal definition layer,reserved for internal use only |
Substrate |
drawing |
40 |
0 |
Substrate recognition layer for LVS |
Substrate |
text |
40 |
25 |
Substrate recognition text for LVS |
dfpad |
drawing |
41 |
0 |
Pad recognition layer |
dfpad |
pillar |
41 |
35 |
Copper pillar pad recognition layer |
dfpad |
sbump |
41 |
36 |
Solder bump pad recognition layer |
ThickGateOx |
drawing |
44 |
0 |
Thick Gate Oxide |
PLDB |
drawing |
45 |
0 |
Reserved for internal LDMOS development |
PWell |
drawing |
46 |
0 |
Reserved for internal use |
PWell |
pin |
46 |
2 |
Pwell pin layer |
PWell |
block |
46 |
21 |
Defines areas where no well implants are allowed PWL:=NOT(NWell OR PWell::Block) |
IC |
drawing |
48 |
0 |
Reserved for internal use |
Via3 |
drawing |
49 |
0 |
Defines 3-rd metal to 4-th metal contact |
Metal4 |
drawing |
50 |
0 |
Defines 4-th metal interconnect |
Metal4 |
pin |
50 |
2 |
Metal4 pin layer |
Metal4 |
mask |
50 |
20 |
added to Metal4: drawing at mask generation |
Metal4 |
filler |
50 |
22 |
Metal4filler layer |
Metal4 |
nofill |
50 |
23 |
Metal4filler exclusion layer |
Metal4 |
slit |
50 |
24 |
Metal4slit definition layer |
Metal4 |
text |
50 |
25 |
Text layer for Metal4, used for LVS |
Metal4 |
OPC |
50 |
26 |
Metal4 OPC definition layer |
Metal4 |
noqrc |
50 |
28 |
No parasitics extraction |
Metal4 |
res |
50 |
29 |
Wire resistor |
Metal4 |
iprobe |
50 |
33 |
Current probe |
Metal4 |
diffprb |
50 |
34 |
Differential Current probe |
HeatTrans |
drawing |
51 |
0 |
Defines heat source for transistors |
HeatRes |
drawing |
52 |
0 |
Defines heat source for resistors |
FBE |
drawing |
54 |
0 |
Fluidic back side etch |
EmPoly |
drawing |
55 |
0 |
Defines npn emitter poly region and pnp basepoly region |
DigiSub |
drawing |
60 |
0 |
Substrate recognition layer for LVS |
NoDRC |
drawing |
62 |
0 |
Excludes areas from design rule checking. Designs with NoDRC are rejected! |
TEXT |
drawing |
63 |
0 |
Macro cell name, element text layer |
Via4 |
drawing |
66 |
0 |
Defines 4-th metal to 5-th metal contact |
Metal5 |
drawing |
67 |
0 |
Defines 5-th metal interconnect |
Metal5 |
pin |
67 |
2 |
Metal5 pin layer |
Metal5 |
mask |
67 |
20 |
added to Metal5: drawing at mask generation |
Metal5 |
filler |
67 |
22 |
Metal5 filler layer |
Metal5 |
nofill |
67 |
23 |
Metal5 filler exclusion layer |
Metal5 |
slit |
67 |
24 |
Metal5 slit definition layer |
Metal5 |
text |
67 |
25 |
Text layer for Metal5 |
Metal5 |
OPC |
67 |
26 |
Metal5 OPC definition layer |
Metal5 |
noqrc |
67 |
28 |
No parasitics extraction |
Metal5 |
res |
67 |
29 |
Wire resistor |
Metal5 |
iprobe |
67 |
33 |
Current probe |
Metal5 |
diffprb |
67 |
34 |
Differential Current probe |
RadHard |
drawing |
68 |
0 |
Defines regions where special radiation hard design rules are applied |
MemCap |
drawing |
69 |
0 |
Defines position of RFMEMS cap |
Varicap |
drawing |
70 |
0 |
Well implant for varicap devices |
IntBondVia |
drawing |
72 |
0 |
Via on top of interposer’s TopMetal2 |
IntBondMet |
drawing |
73 |
0 |
Metal connected to IntBondVia |
DevBondVia |
drawing |
74 |
0 |
Via on top of device’s TopMetal2 |
DevBondMet |
drawing |
75 |
0 |
Metal connected to DevBondVia |
DevTrench |
drawing |
76 |
0 |
Deep trench from front side for plasma dicing approach |
Redist |
drawing |
77 |
0 |
Redistribution layer for metal wiring after chip IO |
GraphBot |
drawing |
78 |
0 |
1st graphene layer |
GraphTop |
drawing |
79 |
0 |
2nd graphene layer |
AntVia1 |
drawing |
83 |
0 |
Deep via between TopMetal2 and AntMetal1 |
AntMetal2 |
drawing |
84 |
0 |
Extra second-metal layer for antenna and passive integration |
GraphCont |
drawing |
85 |
0 |
GraphBot, GraphTop and GraphGat to GraphMetal1 or GraphMet1L contact |
SiWG |
drawing |
86 |
0 |
Backend integrated Si waveguide |
SiWG |
filler |
86 |
22 |
SiWG filler layer |
SiWG |
nofill |
86 |
23 |
SiWG filler exclusion layer |
SiGrating |
drawing |
87 |
0 |
Si waveguide etching layer |
SiNGrating |
drawing |
88 |
0 |
SiN waveguide etching layer |
GraphPas |
drawing |
89 |
0 |
Additional passivation for graphene structures |
EmWind3 |
drawing |
90 |
0 |
Defines G3 npn emitter window |
EmWiHV3 |
drawing |
91 |
0 |
Defines G3 HV npn emitter window |
RedBuLay |
drawing |
92 |
0 |
Burried Layer with reduced dose for isolated NLDMOS |
SMOS |
drawing |
93 |
0 |
Extraction recognition layer for special CMOS devices |
GraphPad |
drawing |
97 |
0 |
Passivation opening |
Polimide |
drawing |
98 |
0 |
Reserved for future use |
Polimide |
pin |
98 |
2 |
Polimide pin layer |
Recog |
drawing |
99 |
0 |
general device recognition shape for device extraction |
Recog |
pin |
99 |
2 |
General device pin recognition layer |
Recog |
esd |
99 |
30 |
ESD device recognition layer |
Recog |
diode |
99 |
31 |
Active diode recognition layer |
Recog |
tsv |
99 |
32 |
TSV device recognition layer |
Recog |
iprobe |
99 |
33 |
Current probe |
Recog |
diffprb |
99 |
34 |
Differential Current probe |
Recog |
pillar |
99 |
35 |
Copper pillar pad recognition layer |
Recog |
sbump |
99 |
36 |
Solder bump pad recognition layer |
Recog |
otp |
99 |
37 |
OTP device recognition layer |
Recog |
pdiode |
99 |
38 |
Enables extraction of parasitic diodes |
Recog |
mom |
99 |
39 |
Metal-on-metal (MOM) capacitor recognition layer |
Recog |
pcm |
99 |
100 |
Process control structure recognition layer |
ColOpen |
drawing |
101 |
0 |
Defines additional collector opening in SG13 HBTs |
GraphMetal1 |
drawing |
109 |
0 |
Graphene-metal standard interconnect |
GraphMetal1 |
filler |
109 |
22 |
GraphMetal1 filler layer |
GraphMetal1 |
nofill |
109 |
23 |
GraphMetal1 filler exclusion layer |
GraphMetal1 |
slit |
109 |
24 |
GraphMetal1 slit definition layer |
GraphMetal1 |
OPC |
109 |
26 |
Graphene-metal opc |
GraphMet1L |
drawing |
110 |
0 |
Graphene-metal lift-off interconnect |
GraphMet1L |
filler |
110 |
22 |
GraphMet1L filler layer |
GraphMet1L |
nofill |
110 |
23 |
GraphMet1L filler exclusion layer |
GraphMet1L |
slit |
110 |
24 |
GraphMet1L slit definition layer |
GraphMet1L |
OPC |
110 |
26 |
Graphene-metal lift-off opc |
EXTBlock |
drawing |
111 |
0 |
Block tip and halo implants |
NLDD |
drawing |
112 |
0 |
Dedicated pwell body for NLDMOS |
PLDD |
drawing |
113 |
0 |
Dedicated nwell body for PLDMOS |
NExt |
drawing |
114 |
0 |
Reserved for internal LDMOS development |
PExt |
drawing |
115 |
0 |
Reserved for internal use |
NExtHV |
drawing |
116 |
0 |
Reserved for internal use |
PExtHV |
drawing |
117 |
0 |
Reserved for internal use |
GraphGate |
drawing |
118 |
0 |
Graphene GFET gate |
SiNWG |
drawing |
119 |
0 |
Backend integrated SiN waveguide |
SiNWG |
filler |
119 |
22 |
SiNWG filler layer |
SiNWG |
nofill |
119 |
23 |
SiNWG filler exclusion layer |
MEMPAD |
drawing |
124 |
0 |
Dedicated to open Pads in RF-MEMS module |
TopVia1 |
drawing |
125 |
0 |
Defines 3-rd (or 5-th) metal to TopMetal1 contact |
TopMetal1 |
drawing |
126 |
0 |
Defines 1-st thick TopMetal layer |
TopMetal1 |
pin |
126 |
2 |
TopMetal1 pin layer |
TopMetal1 |
mask |
126 |
20 |
Added to TopMetal1: drawing at mask generation |
TopMetal1 |
filler |
126 |
22 |
TopMetal1 filler layer |
TopMetal1 |
nofill |
126 |
23 |
TopMetal1 filler exclusion layer |
TopMetal1 |
slit |
126 |
24 |
TopMetal1 slit definition layer |
TopMetal1 |
text |
126 |
25 |
Text layer forTopMetal1, used for LVS |
TopMetal1 |
noqrc |
126 |
28 |
No parasitics extraction |
TopMetal1 |
res |
126 |
29 |
Wire resistor |
TopMetal1 |
iprobe |
126 |
33 |
Current probe |
TopMetal1 |
diffprb |
126 |
34 |
Differential Current probe |
INLDPWL |
drawing |
127 |
0 |
Dedicated PWell body for isolated NLDMOS |
PolyRes |
drawing |
128 |
0 |
used to mark net resistors |
PolyRes |
pin |
128 |
2 |
Defines polysilicon gates and interconnect |
Vmim |
drawing |
129 |
0 |
used to mark net mim capacitors |
nBuLayCut |
drawing |
131 |
0 |
P-separation implat INLDMOS (internal use) |
AntMetal1 |
drawing |
132 |
0 |
Extra first-metal layer for antenna and passive integration |
TopVia2 |
drawing |
133 |
0 |
Defines via between TopMetal1 and TopMetal2 |
TopMetal2 |
drawing |
134 |
0 |
Defines 2-nd thick TopMetal layer |
TopMetal2 |
pin |
134 |
2 |
TopMetal2 pin layer |
TopMetal2 |
mask |
134 |
20 |
added to TopMetal2: drawing at mask generation |
TopMetal2 |
filler |
134 |
22 |
Top Metal2 filler layer |
TopMetal2 |
nofill |
134 |
23 |
Top Metal2 filler exclusion layer |
TopMetal2 |
slit |
134 |
24 |
TopMetal2 slit definition layer |
TopMetal2 |
text |
134 |
25 |
Text layer forTopMetal2 |
TopMetal2 |
noqrc |
134 |
28 |
No parasitics extraction |
TopMetal2 |
res |
134 |
29 |
Wire resistor |
TopMetal2 |
iprobe |
134 |
33 |
Current probe |
TopMetal2 |
diffprb |
134 |
34 |
Differential Current probe |
SNSRing |
drawing |
135 |
0 |
Sensor package ring |
Sensor |
drawing |
136 |
0 |
Sensor recognition layer |
SNSArms |
drawing |
137 |
0 |
Arms of the Sensor |
SNSCMOSVia |
drawing |
138 |
0 |
Defines via between BiCMOS wafer and sensor |
ColWind |
drawing |
139 |
0 |
Defines enclosed active transistor region |
FLM |
drawing |
142 |
0 |
Defines fluidic channel |
HafniumOx |
drawing |
143 |
0 |
MEMRES dielectric layer |
MEMVia |
drawing |
145 |
0 |
Local Vias within RFM area |
ThinFilmRes |
drawing |
146 |
0 |
ThinFilmRes(V) and recognition layer for RFMEMS |
RFMEM |
drawing |
147 |
0 |
Areas for integrated RFMEMS devices |
NoRCX |
drawing |
148 |
0 |
No parasitics extraction |
NoRCX |
m2m3 |
148 |
41 |
No parasitics extraction in Metal2 and Metal3 |
NoRCX |
m2m4 |
148 |
42 |
No parasitics extraction in Metal2 and Metal4 |
NoRCX |
m2m5 |
148 |
43 |
No parasitics extraction in Metal2 and Metal5 |
NoRCX |
m2tm1 |
148 |
44 |
No parasitics extraction in Metal2 and TopMetal1 |
NoRCX |
m2tm2 |
148 |
45 |
No parasitics extraction in Metal2 and TopMetal2 |
NoRCX |
m3m4 |
148 |
46 |
No parasitics extraction in Metal3 and Metal4 |
NoRCX |
m3m5 |
148 |
47 |
No parasitics extraction in Metal3 and Metal5 |
NoRCX |
m3tm1 |
148 |
48 |
No parasitics extraction in Metal3 and TopMetal1 |
NoRCX |
m3tm2 |
148 |
49 |
No parasitics extraction in Metal3 and TopMetal2 |
NoRCX |
m4m5 |
148 |
50 |
No parasitics extraction in Metal4 and Metal5 |
NoRCX |
m4tm1 |
148 |
51 |
No parasitics extraction in Metal4 and TopMetal1 |
NoRCX |
m4tm2 |
148 |
52 |
No parasitics extraction in Metal4 and TopMetal2 |
NoRCX |
m5tm1 |
148 |
53 |
No parasitics extraction in Metal5 and TopMetal1 |
NoRCX |
m5tm2 |
148 |
54 |
No parasitics extraction in Metal5 and TopMetal2 |
NoRCX |
tm1tm2 |
148 |
55 |
No parasitics extraction in TopMetal1and TopMetal2 |
NoRCX |
m1sub |
148 |
123 |
No parasitics extraction in Metal1 and Substrate |
NoRCX |
m2sub |
148 |
124 |
No parasitics extraction in Metal2 and Substrate |
NoRCX |
m3sub |
148 |
125 |
No parasitics extraction in Metal3 and Substrate |
NoRCX |
m4sub |
148 |
126 |
No parasitics extraction in Metal4 and Substrate |
NoRCX |
m5sub |
148 |
127 |
No parasitics extraction in Metal5 and Substrate |
NoRCX |
tm1sub |
148 |
300 |
No parasitics extraction in TopMetal1 and Substrate |
NoRCX |
tm2sub |
148 |
301 |
No parasitics extraction in TopMetal2 and Substrate |
SNSBotVia |
drawing |
149 |
0 |
Sensor bottom via |
SNSTopVia |
drawing |
151 |
0 |
Sensor top via |
DeepVia |
drawing |
152 |
0 |
Through Silicon Via |
FGEtch |
drawing |
153 |
0 |
At this place the 1-st poly-Si layer (floating-gate) is etched before the 2-nd poly-Si layer (control-gate) is deposited |
CtrGat |
drawing |
154 |
0 |
This layer patterns the 2-nd poly-Si layer (control-gate) |
FGImp |
drawing |
155 |
0 |
Defines areas where the Floating-gate is doped and the p-well of the flash-cells is formed |
EmWiHV |
drawing |
156 |
0 |
EmWind layer for high voltage HBT |
LBE |
drawing |
157 |
0 |
For localized back side etch |
AlCuStop |
drawing |
159 |
0 |
Reserved for internal use |
NoMetFiller |
drawing |
160 |
0 |
Exclude all metall filler |
prBoundary |
drawing |
189 |
0 |
Defines boundary of layout cells |
Exchange0 |
drawing |
190 |
0 |
Support layer for layout data exchange (not used in mask preparation) |
Exchange0 |
pin |
190 |
2 |
pin layer of Exchange0 |
Exchange0 |
text |
190 |
25 |
Text layer of Exchange0 |
Exchange1 |
drawing |
191 |
0 |
Support layer for layout data exchange (not used in mask preparation) |
Exchange1 |
pin |
191 |
2 |
pin layer of Exchange1 |
Exchange1 |
text |
191 |
25 |
Text layer of Exchange1 |
Exchange2 |
drawing |
192 |
0 |
Support layer for layout data exchange (not used in mask preparation) |
Exchange2 |
pin |
192 |
2 |
pin layer of Exchange2 |
Exchange2 |
text |
192 |
25 |
Text layer of Exchange2 |
Exchange3 |
drawing |
193 |
0 |
Support layer for layout data exchange (not used in mask preparation) |
Exchange3 |
pin |
193 |
2 |
pin layer of Exchange3 |
Exchange3 |
text |
193 |
25 |
Text layer of Exchange3 |
Exchange4 |
drawing |
194 |
0 |
Support layer for layout data exchange (not used in mask preparation) |
Exchange4 |
pin |
194 |
2 |
pin layer of Exchange4 |
Exchange4 |
text |
194 |
25 |
Text layer of Exchange4 |
isoNWell |
drawing |
257 |
0 |
Defines regions with alternative NWell implant to form isolated NWell |