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TODO: verification/pex/magic
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IHP-GmbH/IHP-Open-PDK
IHP OpenPDK 2bd52f0 documentation
Physical & Design Verification
Parasitics Extraction (PEX)
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IHP 130nm BiCMOS Open Source PDK
IHP-GmbH/IHP-Open-PDK
PDK Contents
1. Libraries
1.1. Reference Libraries
1.2. Technology Libraries
1.3. Creating New Libraries
1.4. IO and Periphery Library (sg13g2_io)
1.4.1. Available Cells
1.4.2. Output Drive Strength
1.4.3. Choosing the Right Drive Strength
1.4.4. Pin Interface
Installation
1. Dependencies
1.1. Build tools
1.2. Useful tools
1.3. Build dependencies
2. Installation
2.1. Requirements
2.2. Cloning
2.3. General configuration
2.4. Verilog-A models compilation
2.5. Tool specific configuration
3. PDK Module Interface
3.1. What the implementation does
3.2. Code references
3.3. Practical takeaway
Process Specifications
1. General Information
1.1. Main Processing Sequence and Cross-Section Schematic
1.2. Process Control
1.2.1. Pass/Fail Parameters
1.2.2. Information Parameters
1.3. Wafer Reject Criteria
2. Process Control Parameters
2.1. NMOS-Specs
2.2. PMOS-Specs
2.3. iNMOS-Specs
2.4. HV-NMOS-Specs
2.5. HV-PMOS-Specs
2.6. HV-iNMOS-Specs
2.7. Rsil-Specs
2.8. Rppd-Specs
2.9. Rhigh-Specs
2.10. Schottky_nbl1-Specs
2.11. S-Varicap-Specs
2.12. MIM Capacitor-Specs
2.13. Resistances, Line Width Deltas, Temperature Coefficients
2.14. Contact & Via Resistances
2.15. Maximum Current Densities
2.16. Layer Thickness Values
2.17. Parasitic Capacitances
3. Bipolar Parameters
3.1. npn13g2-Specs
3.2. npn13g2l-Specs
3.3. npn13g2v-Specs
4. Attachment A: Measurement Conditions
5. Change History
6. Known Issues
Layout Rules
1. General
1.1. Scope
1.2. List of abbreviations
1.3. Layout Information
1.4. Reference documents
2. Layer Table
Analog Design
1. Analog/Mixed/RF flow
2. Schematic capture with XSCHEM
2.1. XSCHEM installation and configuration
2.2. XSCHEM symbol library
2.3. XSCHEM testcases
2.4. XSCHEM standard cell library
2.5. XSCHEM IO cell library
3. Schematic capture with QUCS-S
3.1. Adding a new library and objects to Qucs-S via XML interface
3.2. Using Qucs-S with IHP-Open-PDK
4. Simulations using ngspice
4.1. NGSPICE installation
4.2. NGSPICE basic testcases
5. Simulations using Xyce
5.1. Xyce installation on Ubuntu LTS (22.04 and newer)
5.1.1. Trilinos installation
5.1.2. ADMS installation
5.1.3. XYCE installation
6. Simulations using Gnucap
6.1. Introduction to Gnucap
6.2. Gnucap and gnucap-modelgen-verilog installation on ubuntu 22.04 LTS
6.3. Gnucap basic example
6.4. Compiling a Verilog-A model to be used in a simulation
6.5. References
7. Analog design using pygmid tool
7.1. Pygmid installation and configuration
7.2. Device characterization using pygmid
7.3. Basic usage of pygmid
8. Analog design using KLayout tool
9. Layout with GDSFactory
9.1. Advantages over manual layout
9.2. Getting started
Digital Design
With OpenROAD
LibreLane Setup Guide
Prerequisites
Quick Start
PDK Configuration
Automatic PDK Management (Recommended)
Manual PDK Installation (Optional)
Next Steps
Additional Resources
With LibreLane
Creating the Files
Running the Flow
View Your Design
Using OpenROAD GUI
Using KLayout
Discover the
run/
Directory
Further Resources
Full Chip Design With Librelane
Chip Finishing
1. Filler Generation
2. KLayout
2.1. Controlling Metal Filler Densities
2.2. Verification
3. gdsfill
3.1. Installation
3.2. Density
3.3. Erase
3.4. Fill
3.5. Custom Configuration
Physical & Design Verification
Design Rule Checking (DRC)
1. Precheck (Minimal) DRC rules
1.1. Activ (not in BEOL)
1.2. Activ Filler (not in BEOL)
1.3. Thick Gate Oxide (not in BEOL)
1.4. GatPoly (not in BEOL)
1.5. GatPoly Filler (not in BEOL)
1.6. Cont (not in BEOL)
1.7. Metal
1.8. Metal Filler
1.9. Via
1.10. TopVia1
1.11. TopMetal1
1.12. TopVia2
1.13. TopMetal2
1.14. TopMetal Filler
1.15. Passiv
1.16. Density rules
1.17. LBE
1.18. Pad Dimensions
1.19. Sealring
1.20. Pin layer rules
1.21. Forbidden layers
2. Main DRC rules
3. Extra DRC rules
4. Klayout-DRC
4.1. Folder Structure
4.2. Prerequisites
4.3. Installation
4.4. Usage
4.5. DRC Testing
5. TODO: verification/drc/magic
Layout Versus Schematic (LVS) Checking
1. General
1.1. Purpose
1.2. Abbreviations
1.3. Derived Layers
1.4. Glossary of Terms
2. Layers
2.1. Layers Definition
2.2. Layout Layers
3. Truth Table for SG13G2 SiGe BiCMOS Process
4. Devices
4.1. MOSFET Devices
4.2. RFMOSFET Devices
4.3. BJT Devices
4.4. Diode Devices
4.5. Resistor Devices
4.6. Capacitor Devices
4.7. ESD Devices
4.8. Inductor Devices
4.9. Tap Devices
5. Klayout-LVS
5.1. Folder Structure
5.2. Prerequisites
5.3. Installation
5.4. Usage
5.5. LVS Testing
6. Magic-LVS
Parasitic Extraction (PEX)
With Magic
EM Simulation
EM Simulation Overview
Introduction
Solver methods
Which solver method is better for my model?
Workflows using Python model script
Graphical user interface: EMStudio
Graphical user interface: setupEM
S-Parameter port de-embedding
Port de-embedding in Palace workflow
Port de-embedding in openEMS workflow
Lumped model and SPICE model extraction
Lumped model fit
Black box vector fit
Viewing S-simulation results
S-parameter viewer in qucs-s
Python script „plot_snp“
Python script „plot_inductor“
GDSII geometry cleanup prior to simulation
gds_removefill
gds_simplify
gds_prepare_for_EM
Some example simulations
mpa_core
Inductor 400pH @ 40 GHz
Butler matrix 93 GHz
Stacked Technology using openEMS flow
Contribution
1. ContributionModel
1.1. Developer Certificate of Origin
1.2. Code reviews
1.3. Community Guidelines
2. Workflow
References
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TODO: verification/pex/magic
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