1. Precheck (Minimal) DRC rules
Tip
These are used for rejection tests during the pre-tapeout checks.
1.1. Activ (not in BEOL)
Name |
Description |
Value (um) |
|---|---|---|
Act.a |
Min. Activ width |
0.15 |
Act.b |
Min. Activ space or notch |
0.21 |
1.2. Activ Filler (not in BEOL)
Name |
Description |
Value (um) |
|---|---|---|
AFil.c1 |
AFil.c1 Min. Activ:filler space to Activ |
0.42 |
1.3. Thick Gate Oxide (not in BEOL)
Name |
Description |
Value (um) |
|---|---|---|
TGO.f |
Min. ThickGateOx width |
0.86 |
1.4. GatPoly (not in BEOL)
Name |
Description |
Value (um) |
|---|---|---|
Gat.a |
Min. GatPoly width |
0.13 |
Gat.b |
Min. GatPoly space or notch |
0.18 |
Gat.d |
Min. GatPoly space to Activ |
0.07 |
1.5. GatPoly Filler (not in BEOL)
Name |
Description |
Value (um) |
|---|---|---|
GFil.d |
GFil.d Min. GatPoly:filler space to Activ, GatPoly, Cont, pSD, nSD:block, SalBlock |
1.1 |
1.6. Cont (not in BEOL)
Name |
Description |
Value (um) |
|---|---|---|
Cnt.a |
Min. and max. Cont width |
0.16 |
Cnt.b |
Min. Cont space |
0.18 |
1.7. Metal
Name |
Description |
Value (um) |
|---|---|---|
M1.a |
Min. Metal1 width |
0.16 |
M1.b |
Min. Metal1 space or notch |
0.18 |
M2.a |
Min. Metal2 width |
0.2 |
M2.b |
Min. Metal2 space or notch |
0.21 |
M3.a |
Min. Metal3 width |
0.2 |
M3.b |
Min. Metal3 space or notch |
0.21 |
M4.a |
Min. Metal4 width |
0.2 |
M4.b |
Min. Metal4 space or notch |
0.21 |
M5.a |
Min. Metal5 width |
0.2 |
M5.b |
Min. Metal5 space or notch |
0.21 |
1.8. Metal Filler
Name |
Description |
Value (um) |
|---|---|---|
M1Fil.c |
M1Fil.c Min. Metal1:filler space to Metal1 |
0.42 |
M2Fil.c |
M2Fil.c Min. Metal2:filler space to Metal2 |
0.42 |
M3Fil.c |
M3Fil.c Min. Metal3:filler space to Metal3 |
0.42 |
M4Fil.c |
M4Fil.c Min. Metal4:filler space to Metal4 |
0.42 |
M5Fil.c |
M5Fil.c Min. Metal5:filler space to Metal5 |
0.42 |
1.9. Via
Name |
Description |
Value (um) |
|---|---|---|
V1.a |
Min. and max. Via1 width |
0.19 |
V1.b |
Min. Via1 space |
0.22 |
V2.a |
Min. and max. Via2 width |
0.19 |
V2.b |
Min. Via2 space |
0.22 |
V3.a |
Min. and max. Via3 width |
0.19 |
V3.b |
Min. Via3 space |
0.22 |
V4.a |
Min. and max. Via4 width |
0.19 |
V4.b |
Min. Via4 space |
0.22 |
1.10. TopVia1
Name |
Description |
Value (um) |
|---|---|---|
TV1.a |
Min. and max. TopVia1 width |
0.42 |
TV1.b |
Min. TopVia1 space |
0.42 |
1.11. TopMetal1
Name |
Description |
Value (um) |
|---|---|---|
TM1.a |
Min. TopMetal1 width |
1.64 |
TM1.b |
Min. TopMetal1 space or notch |
1.64 |
1.12. TopVia2
Name |
Description |
Value (um) |
|---|---|---|
TV2.a |
Min. and max. TopVia2 width |
0.9 |
TV2.b |
Min. TopVia2 space |
1.06 |
1.13. TopMetal2
Name |
Description |
Value (um) |
|---|---|---|
TM2.a |
Min. TopMetal2 width |
2 |
TM2.b |
Min. TopMetal2 space or notch |
2 |
1.14. TopMetal Filler
Name |
Description |
Value (um) |
|---|---|---|
TM1Fil.c |
TM1Fil.c Min. TopMetal1:filler space to TopMetal1 |
3 |
TM2Fil.c |
5.26. TM2Fil.c Min. TopMetal2:filler space to TopMetal2 |
3 |
1.15. Passiv
Name |
Description |
Value (um) |
|---|---|---|
Pas.a |
Min. Passiv width |
2.1 |
Pas.b |
Min. Passiv space or notch |
3.5 |
1.16. Density rules
1.16.1. Front-end density rules
Name |
Description |
Value (um) |
|---|---|---|
GFil.g |
GFil.g Min. global GatPoly density [%] |
15 |
AFil.g |
AFil.g Min. global Activ density [%] |
35 |
AFil.g1 |
AFil.g1 Max. global Activ density [%] |
55 |
AFil.g2 |
AFil.g2 Min. Activ coverage ratio for any 800 x 800 µm² chip area [%] |
25 |
AFil.g3 |
AFil.g3 Max. Activ coverage ratio for any 800 x 800 µm² chip area [%] |
65 |
1.16.2. Back-end density rules
Name |
Description |
Value (um) |
|---|---|---|
M1.j |
Min. global Metal1 density [%] |
35 |
M1.k |
Max. global Metal1 density [%] |
60 |
M2.j |
Min. global Metal2 density [%] |
35 |
M2.k |
Max. global Metal2 density [%] |
60 |
M3.j |
Min. global Metal3 density [%] |
35 |
M3.k |
Max. global Metal3 density [%] |
60 |
M4.j |
Min. global Metal4 density [%] |
35 |
M4.k |
Max. global Metal4 density [%] |
60 |
M5.j |
Min. global Metal5 density [%] |
35 |
M5.k |
Max. global Metal5 density [%] |
60 |
M1Fil.h |
Min. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%] |
25 |
M1Fil.k |
Max. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%] |
75 |
M2Fil.h |
Min. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%] |
25 |
M2Fil.k |
Max. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%] |
75 |
M3Fil.h |
Min. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%] |
25 |
M3Fil.k |
Max. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%] |
75 |
M4Fil.h |
Min. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%] |
25 |
M4Fil.k |
Max. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%] |
75 |
M5Fil.h |
Min. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%] |
25 |
M5Fil.k |
Max. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%] |
75 |
TM1.c |
Min. global TopMetal1 density [%] |
25 |
TM1.d |
Max. global TopMetal1 density [%] |
75 |
TM2.c |
Min. global TopMetal2 density [%] |
25 |
TM2.d |
Max. global TopMetal2 density [%] |
75 |
1.17. LBE
Name |
Description |
Value (um) |
|---|---|---|
LBE.a |
Min. LBE width |
100 |
LBE.b |
Max. LBE width |
1500 |
LBE.b1 |
Max. LBE area (µm²) |
250000 |
LBE.c |
Min. LBE space or notch |
100 |
LBE.d |
Min. LBE space to inner edge of EdgeSeal |
150 |
LBE.h |
No LBE ring allowed |
|
LBE.i |
Max. global LBE density [%] |
20 |
1.18. Pad Dimensions
Name |
Description |
Value (um) |
|---|---|---|
Pad.m |
SBumpPad and CuPillarPad in same layout not allowed |
1.18.1. Solder Bump Rules
Name |
Description |
Value (um) |
|---|---|---|
Padb.a |
Min. SBumpPad size |
60 |
Padb.b |
Min. SBumpPad space |
70 |
Padb.c |
Min. TopMetal2 (within dfpad) enclosure of SBumpPad |
10 |
1.18.2. Copper Pillar Rules
Name |
Description |
Value (um) |
|---|---|---|
Padc.a |
Min. CuPillarPad size |
35 |
Padc.b |
Min. CuPillarPad space |
40 |
Padc.c |
Min. TopMetal2 (within dfpad) enclosure of CuPillarPad |
7.5 |
1.19. Sealring
Name |
Description |
Value (um) |
|---|---|---|
Seal.l |
No structures outside sealring boundary allowed |
|
Seal.n |
Sealring must be enclosed by an unbroken Passiv ring |
1.20. Pin layer rules
Name |
Description |
Value (um) |
|---|---|---|
Pin.a |
Min. Activ enclosure of Activ:pin |
0 |
Pin.b |
Min. GatPoly enclosure of GatPoly:pin |
0 |
Pin.e |
Min. Metal1 enclosure of Metal1:pin |
0 |
Pin.f.M2 |
Min. Metal2 enclosure of Metal2:pin |
0 |
Pin.f.M3 |
Min. Metal3 enclosure of Metal3:pin |
0 |
Pin.f.M4 |
Min. Metal4 enclosure of Metal4:pin |
0 |
Pin.f.M5 |
Min. Metal5 enclosure of Metal5:pin |
0 |
Pin.g |
Min. TopMetal1 enclosure of TopMetal1:pin |
0 |
Pin.h |
Min. TopMetal2 enclosure of TopMetal2:pin |
0 |
1.21. Forbidden layers
Name |
Description |
Value (um) |
|---|---|---|
forbidden.BiWind |
forbidden.BiWind BiWind is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.PEmWind |
forbidden.PEmWind PEmWind is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.BasPoly |
forbidden.BasPoly BasPoly is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.DeepCo |
forbidden.DeepCo DeepCo is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.PEmPoly |
forbidden.PEmPoly PEmPoly is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.EmPoly |
forbidden.EmPoly EmPoly is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.LDMOS |
forbidden.LDMOS LDMOS is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.PBiWind |
forbidden.PBiWind PBiWind is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.NoDRC |
forbidden.NoDRC NoDRC is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.Flash |
forbidden.Flash Flash is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.ColWind |
forbidden.ColWind ColWind is forbidden in designs submitted for all 0.13 µm technologies. |
Total: 110