3. Truth Table for SG13G2 SiGe BiCMOS Process

The Topological Truth Table is a design aid that helps establish the relationship between:

  • IHP-defined topological layers: These are the fundamental building blocks used to construct an integrated circuit (IC) layout.

  • Discrete structures: These are individual elements within the IC, such as transistors, resistors, and capacitors.

Note

The table serves two primary purposes:

  • Verifying implant layer generation: This table can be used to ensure that the specified implants are correctly applied to various discrete structures.

  • Understanding layer-structure interactions: clarifies how each topological layer interacts with different structures.

Here’s an explanation of the symbols used in the table:

0: The topological level must not touch the structure.

1: The topological level must either enclose or match the structure.

X: The layer has no electrical impact on the structure.

By effectively utilizing the Topological Truth Table, designers can ensure accurate and efficient layout creation within the integrated circuit design process.

Truth Table for SG13G2 SiGe BiCMOS Process

Device/Layer

Activ

GatPoly

Nwell

Pwell

Pwell.block

nsD.drw

nsD

nsD.block

pSD

Nwell_holes

ptap_holes

ntap_holes

nBuLay

ThickGateOx

TRANS

EmWind

EmWiHV

SalBlock

PolyRes

MIM

Metal5

TopMetal1

TopMetal2

EXTBlock

RES

Metal1.res

Activ.mask

ContBar

Recog.diode

Recog.esd

IND

IND.pin

substrate

text

1- MOS:

nmos

1

1

0

1

0

0

1

0

0

x

x

x

x

0

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

0

0

0

0

x

nmosHV

1

1

0

1

0

0

1

0

0

x

x

x

x

1

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

0

0

0

0

x

pmos

1

1

1

0

0

0

0

0

1

0

x

x

x

0

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

0

0

0

0

x

pmosHV

1

1

1

0

0

0

0

0

1

0

x

x

x

1

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

0

0

0

0

x

2- RF-MOS:

rfnmos

1

1

0

1

0

0

1

0

0

x

1

x

0

0

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

0

0

0

0

1

rfnmosHV

1

1

0

1

0

0

1

0

0

x

1

x

0

1

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

0

0

0

0

1

rfpmos

1

1

1

0

0

0

0

0

1

0

x

1

0

0

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

0

0

0

0

1

rfpmosHV

1

1

1

0

0

0

0

0

1

0

x

1

0

1

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

0

0

0

0

1

3- BJT:

npn13G2

1

0

0

1

0

0

1

1

0

x

1

x

0

0

1

1

0

0

0

x

x

x

x

0

0

x

1

x

0

0

0

0

0

x

npn13G2L

1

0

0

1

0

0

1

0

0

x

1

x

0

0

1

1

0

0

0

x

x

x

x

0

0

x

1

x

0

0

0

0

0

x

npn13G2V

1

0

0

1

0

0

1

0

0

x

1

x

0

0

1

0

1

0

0

x

x

x

x

0

0

x

1

x

0

0

0

0

0

x

pnpMPA

1

0

1

0

0

0

1

0

1

0

1

1

1

0

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

0

0

0

0

x

4- Diodes:

dantenna

1

0

0

1

0

0

1

0

0

x

x

x

x

x

0

0

0

0

0

x

x

x

x

0

0

x

0

x

1

0

0

0

0

x

dpantenna

1

0

0

1

0

0

0

0

1

x

x

x

x

x

0

0

0

0

0

x

x

x

x

0

0

x

0

x

1

0

0

0

0

x

schottky_nbl1

1

0

0

0

1

0

1

1

0

1

1

x

1

1

0

0

0

1

0

x

x

x

x

0

0

x

0

1

1

0

0

0

0

x

5- Resistors:

res_rhigh

0

1

x

x

0

1

1

0

1

x

x

x

0

0

0

0

0

1

1

x

x

x

x

1

0

x

0

x

0

0

0

0

0

x

res_rppd

0

1

x

x

0

0

0

0

1

x

x

x

0

0

0

0

0

1

1

x

x

x

x

1

0

x

0

x

0

0

0

0

0

x

res_rsil

0

1

x

x

0

0

1

0

0

x

x

x

0

0

0

0

0

0

1

x

x

x

x

1

1

x

0

x

0

0

0

0

0

x

lvsres

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

1

x

x

x

x

x

x

x

x

6- Capacitors:

cmim

x

x

x

x

0

x

x

x

x

x

x

x

x

x

x

x

x

x

x

1

1

1

x

x

x

x

x

x

x

x

0

0

x

x

rfcmim

x

x

x

0

1

x

x

x

x

x

x

x

x

x

x

x

x

x

x

1

1

1

x

x

x

x

x

x

x

x

0

0

x

x

Svaricap

1

1

1

0

0

0

1

0

0

0

x

x

1

1

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

0

0

0

0

x

7- ESD:

diodevdd_2k

1

0

1

1

0

0

1

0

1

0

1

x

0

0

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

1

0

0

0

x

diodevdd_4k

1

0

1

1

0

0

1

0

1

0

1

x

0

0

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

1

0

0

0

x

diodevss_2k

1

0

0

1

0

0

1

0

1

1

1

x

0

0

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

1

0

0

0

x

diodevss_4k

1

0

0

1

0

0

1

0

1

1

1

x

0

0

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

1

0

0

0

x

idiodevdd_2kv

1

0

1

1

1

0

1

0

1

0

1

x

1

0

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

1

0

0

0

x

idiodevdd_4kv

1

0

1

1

1

0

1

0

1

0

1

x

1

0

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

1

0

0

0

x

idiodevss_2kv

1

0

0

1

0

0

1

0

1

1

1

x

1

0

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

1

0

0

0

x

idiodevss_4kv

1

0

0

1

0

0

1

0

1

1

1

x

1

0

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

1

0

0

0

x

nmoscl_2

1

1

1

1

0

0

1

0

1

1

x

x

1

1

0

0

0

1

0

x

x

x

x

0

0

x

0

x

0

1

0

0

0

1

nmoscl_4

1

1

1

1

0

0

1

0

1

1

x

x

1

1

0

0

0

1

0

x

x

x

x

0

0

x

0

x

0

1

0

0

0

1

scr1

1

1

1

1

0

0

1

1

1

1

x

x

1

1

0

0

0

1

0

x

x

x

x

0

0

x

0

x

0

1

0

0

0

1

8- Inductors:

inductor

x

0

x

0

1

0

x

x

x

x

x

x

0

0

0

0

0

0

0

0

x

x

1

0

0

x

0

x

0

0

1

1

0

1

inductor3

x

0

x

0

1

0

x

x

x

x

x

x

0

0

0

0

0

0

0

0

x

x

1

0

0

x

0

x

0

0

1

1

0

1

9- Taps:

ptap1

1

0

0

1

0

0

0

0

1

x

x

x

x

x

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

0

0

0

1

1

ntap1

1

0

1

0

x

0

1

0

0

0

x

x

x

x

0

0

0

0

0

x

x

x

x

0

0

x

0

x

0

0

0

0

0

1