2. Main DRC rules
Name |
Description |
Value (um2) |
|---|---|---|
NW.b |
Min. NWell space or notch (same net). NWell regions separated by less than this value will be merged. |
0.62 |
NW.b1 |
Min. PWell width between NWell regions (different net) (Note 3) |
1.8 |
PWB.d |
Min. PWell:block overlap of NWell |
0 |
PWB.e |
Min. PWell:block space to (N+Activ not inside ThickGateOx) in PWell |
0.31 |
PWB.e1 |
Min. PWell:block space to (N+Activ inside ThickGateOx) in PWell |
0.62 |
PWB.f |
Min. PWell:block space to (P+Activ not inside ThickGateOx) in PWell |
0.24 |
PWB.f1 |
Min. PWell:block space to (P+Activ inside ThickGateOx) in PWell |
0.62 |
NBL.b |
Min. nBuLay space or notch (same net) |
1.5 |
NBL.c |
Min. PWell width between nBuLay regions (different net) (Note 1) |
3.2 |
NBL.d |
Min. PWell width between nBuLay and NWell (different net) (Note 1) |
2.2 |
NBL.e |
Min. nBuLay space to unrelated N+Activ |
1 |
NBL.f |
Min. nBuLay space to unrelated P+Activ |
0.5 |
Act.a |
Min. Activ width |
0.15 |
Act.b |
Min. Activ space or notch |
0.21 |
AFil.c |
Min. Activ:filler space to Cont, GatPoly |
1.1 |
AFil.c1 |
Min. Activ:filler space to Activ |
0.42 |
AFil.d |
Min. Activ:filler space to NWell, nBuLay |
1 |
AFil.e |
Min. Activ:filler space to TRANS |
1 |
AFil.g |
Min. global Activ density [%] |
35 |
AFil.g1 |
Max. global Activ density [%] |
55 |
AFil.g2 |
Min. Activ coverage ratio for any 800 x 800 µm² chip area [%] |
25 |
AFil.g3 |
Max. Activ coverage ratio for any 800 x 800 µm² chip area [%] |
65 |
AFil.j |
Min. nSD:block and SalBlock enclosure of Activ:filler inside PWell:block |
0.25 |
TGO.f |
Min. ThickGateOx width |
0.86 |
Gat.a |
Min. GatPoly width |
0.13 |
Gat.a1 |
Min. GatPoly width for channel length of 1.2 V NFET |
0.13 |
Gat.a2 |
Min. GatPoly width for channel length of 1.2 V PFET |
0.13 |
Gat.b |
Min. GatPoly space or notch |
0.18 |
Gat.d |
Min. GatPoly space to Activ |
0.07 |
Gat.g |
Min. GatPoly width for 45-degree bent shapes if the bend GatPoly length is > 0.39 um |
0.16 |
GFil.d |
Min. GatPoly:filler space to Activ, GatPoly, Cont, pSD, nSD:block, SalBlock |
1.1 |
GFil.e |
Min. GatPoly:filler space to NWell, nBuLay |
15 |
GFil.g |
Min. global GatPoly density [%] |
15 |
GFil.i |
Max. GatPoly:nofill area (um2) |
400 x 400 |
pSD.c1 |
Min. pSD enclosure of P+Activ in PWell |
0.03 |
Cnt.a |
Min. and max. Cont width |
0.16 |
Cnt.b |
Min. Cont space |
0.18 |
Cnt.c |
Min. Activ enclosure of Cont |
0.07 |
Cnt.d |
Min. GatPoly enclosure of Cont |
0.07 |
Cnt.e |
Min. Cont on GatPoly space to Activ |
0.14 |
Cnt.g1 |
Min. pSD space to Cont on nSD-Activ |
0.09 |
Cnt.g2 |
Min. pSD overlap of Cont on pSD-Activ |
0.09 |
CntB.b1 |
Min. ContBar space with common run > 5 um |
0.36 |
CntB.h1 |
Min. Metal1 enclosure of ContBar |
0.05 |
M1.a |
Min. Metal1 width |
0.16 |
M1.b |
Min. Metal1 space or notch |
0.18 |
M1.e |
Min. space of Metal1 lines if, at least one line is wider than 0.3 um and the parallel run is more than 1.0 um |
0.22 |
M1.f |
Min. space of Metal1 lines if, at least one line is wider than 10.0 um and the parallel run is more than 10.0 um |
0.6 |
M1.g |
Min. 45-degree bent Metal1 width if the bent metal length is > 0.5 um |
0.2 |
M1.i |
Min. space of Metal1 lines of which at least one is bent by 45-degree |
0.22 |
M1.j |
Min. global Metal1 density [%] |
35 |
M1.k |
Max. global Metal1 density [%] |
60 |
M2.a |
Min. Metal2 width |
0.2 |
M2.b |
Min. Metal2 space or notch |
0.21 |
M2.e |
Min. space of Metal2 lines if, at least one line is wider than 0.39 um and the parallel run is more than 1.0 um |
0.24 |
M2.f |
Min. space of Metal2 lines if, at least one line is wider than 10.0 um and the parallel run is more than 10.0 um |
0.6 |
M2.g |
Min. 45-degree bent Metal2 width if the bent metal length is > 0.5 um |
0.24 |
M2.i |
Min. space of Metal2 lines of which at least one is bent by 45-degree |
0.24 |
M2.j |
Min. global Metal2 density [%] |
35 |
M2.k |
Max. global Metal2 density [%] |
60 |
M3.a |
Min. Metal3 width |
0.2 |
M3.b |
Min. Metal3 space or notch |
0.21 |
M3.e |
Min. space of Metal3 lines if, at least one line is wider than 0.39 um and the parallel run is more than 1.0 um |
0.24 |
M3.f |
Min. space of Metal3 lines if, at least one line is wider than 10.0 um and the parallel run is more than 10.0 um |
0.6 |
M3.g |
Min. 45-degree bent Metal3 width if the bent metal length is > 0.5 um |
0.24 |
M3.i |
Min. space of Metal3 lines of which at least one is bent by 45-degree |
0.24 |
M3.j |
Min. global Metal3 density [%] |
35 |
M3.k |
Max. global Metal3 density [%] |
60 |
M4.a |
Min. Metal4 width |
0.2 |
M4.b |
Min. Metal4 space or notch |
0.21 |
M4.e |
Min. space of Metal4 lines if, at least one line is wider than 0.39 um and the parallel run is more than 1.0 um |
0.24 |
M4.f |
Min. space of Metal4 lines if, at least one line is wider than 10.0 um and the parallel run is more than 10.0 um |
0.6 |
M4.g |
Min. 45-degree bent Metal4 width if the bent metal length is > 0.5 um |
0.24 |
M4.i |
Min. space of Metal4 lines of which at least one is bent by 45-degree |
0.24 |
M4.j |
Min. global Metal4 density [%] |
35 |
M4.k |
Max. global Metal4 density [%] |
60 |
M5.a |
Min. Metal5 width |
0.2 |
M5.b |
Min. Metal5 space or notch |
0.21 |
M5.e |
Min. space of Metal5 lines if, at least one line is wider than 0.39 um and the parallel run is more than 1.0 um |
0.24 |
M5.f |
Min. space of Metal5 lines if, at least one line is wider than 10.0 um and the parallel run is more than 10.0 um |
0.6 |
M5.g |
Min. 45-degree bent Metal5 width if the bent metal length is > 0.5 um |
0.24 |
M5.i |
Min. space of Metal5 lines of which at least one is bent by 45-degree |
0.24 |
M5.j |
Min. global Metal5 density [%] |
35 |
M5.k |
Max. global Metal5 density [%] |
60 |
M1Fil.a2 |
Max. Metal1:filler width |
5 |
M1Fil.c |
Min. Metal1:filler space to Metal1 |
0.42 |
M1Fil.h |
Min. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%] |
25 |
M1Fil.k |
Max. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%] |
75 |
M2Fil.a2 |
Max. Metal2:filler width |
5 |
M2Fil.c |
Min. Metal2:filler space to Metal2 |
0.42 |
M2Fil.h |
Min. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%] |
25 |
M2Fil.k |
Max. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%] |
75 |
M3Fil.a2 |
Max. Metal3:filler width |
5 |
M3Fil.c |
Min. Metal3:filler space to Metal3 |
0.42 |
M3Fil.h |
Min. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%] |
25 |
M3Fil.k |
Max. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%] |
75 |
M4Fil.a2 |
Max. Metal4:filler width |
5 |
M4Fil.c |
Min. Metal4:filler space to Metal4 |
0.42 |
M4Fil.h |
Min. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%] |
25 |
M4Fil.k |
Max. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%] |
75 |
M5Fil.a2 |
Max. Metal5:filler width |
5 |
M5Fil.c |
Min. Metal5:filler space to Metal5 |
0.42 |
M5Fil.h |
Min. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%] |
25 |
M5Fil.k |
Max. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%] |
75 |
V1.a |
Min. and max. Via1 width |
0.19 |
V1.b |
Min. Via1 space |
0.22 |
V1.c |
Min. Metal1 enclosure of Via1 |
0.01 |
V2.a |
Min. and max. Via2 width |
0.19 |
V2.b |
Min. Via2 space |
0.22 |
V2.c |
Min. Metal2 enclosure of Via2 |
0.005 |
V3.a |
Min. and max. Via3 width |
0.19 |
V3.b |
Min. Via3 space |
0.22 |
V3.c |
Min. Metal3 enclosure of Via3 |
0.005 |
V4.a |
Min. and max. Via4 width |
0.19 |
V4.b |
Min. Via4 space |
0.22 |
V4.c |
Min. Metal4 enclosure of Via4 |
0.005 |
TV1.a |
Min. and max. TopVia1 width |
0.42 |
TV1.b |
Min. TopVia1 space |
0.42 |
TV1.c |
Min. Metal5 enclosure of TopVia1 |
0.1 |
TV1.d |
Min. TopMetal1 enclosure of TopVia1 |
0.42 |
TM1.a |
Min. TopMetal1 width |
1.64 |
TM1.b |
Min. TopMetal1 space or notch |
1.64 |
TM1.c |
Min. global TopMetal1 density [%] |
25 |
TM1.d |
Max. global TopMetal1 density [%] |
70 |
TM1Fil.a1 |
Max. TopMetal1:filler width |
10 |
TM1Fil.c |
Min. TopMetal1:filler space to TopMetal1 |
3 |
TV2.a |
Min. and max. TopVia2 width |
0.9 |
TV2.b |
Min. TopVia2 space |
1.06 |
TV2.c |
Min. TopMetal1 enclosure of TopVia2 |
0.5 |
TV2.d |
Min. TopMetal2 enclosure of TopVia2 |
0.5 |
TM2.a |
Min. TopMetal2 width |
2 |
TM2.b |
Min. TopMetal2 space or notch |
2 |
TM2.bR |
Min. space of TopMetal2 lines if, at least one line is wider than 5.0 um and the parallel run is more than 50.0 um (Note 1, 2) |
5 |
TM2.c |
Min. global TopMetal2 density [%] |
25 |
TM2.d |
Max. global TopMetal2 density [%] |
70 |
TM2Fil.a1 |
Max. TopMetal2:filler width |
1 |
TM2Fil.c |
Min. TopMetal2:filler space to TopMetal2 |
3 |
Pas.a |
Min. Passiv width |
2.1 |
Pas.b |
Min. Passiv space or notch |
3.5 |
Pas.c |
Min. TopMetal2 enclosure of Passiv (Note 1) |
2.1 |
npn13G2.bR |
Max. recommended total number of npn13G2 emitters per chip |
4000 |
npn13G2L.cR |
Max. recommended total number of npn13G2L emitters per chip |
800 |
npn13G2V.cR |
Max. recommended total number of npn13G2V emitters per chip |
800 |
Sdiod.d |
Min. and max. ContBar width inside nBuLay |
0.3 |
Sdiod.e |
Min. and max. ContBar length inside nBuLay |
1 |
Pad.fR |
Min. recommended Metal(n), TopMetal1, TopMetal2 exit length |
7 |
Pad.i |
dfpad without TopMetal2 not allowed |
|
Padb.a |
SBumpPad size |
60 |
Padb.b |
Min. SBumpPad space |
70 |
Padb.c |
Min. TopMetal2 (within dfpad) enclosure of SBumpPad |
10 |
Padb.d |
Min. SBumpPad space to EdgeSeal |
50 |
Padc.a |
CuPillarPad size |
35 |
Padc.b |
Min. CuPillarPad space |
40 |
Padc.c |
Min. TopMetal2 (within dfpad) enclosure of CuPillarPad |
7.5 |
Seal.b |
Min. Activ space to EdgeSeal-Activ, EdgeSeal-pSD, EdgeSeal-Metal(n=1-5), EdgeSeal-TopMetal1, EdgeSeal-TopMetal2 |
4.9 |
Seal.k |
Min. EdgeSeal 45-degree corner length (Note 1) |
21 |
Seal.l |
No structures outside sealring boundary allowed |
|
Seal.m |
Only one sealring per chip allowed (Note 1) |
|
Seal.n |
seal.n Sealring must be enclosed by an unbroken Passiv ring |
|
MIM.c |
Min. Metal5 enclosure of MIM |
0.6 |
MIM.d |
Min. MIM enclosure of TopVia1 |
0.36 |
MIM.gR |
Max. recommended total MIM area per chip (um2) |
174800 |
Ant.a |
Max. ratio of GatPoly over field oxide area to connected Gate area |
200 |
Ant.b |
Max. ratio of cumulative metal area (from Metal1 to TopMetal2) to connected Gate area (without protection diode) |
200 |
Ant.c |
Max. ratio of Cont area to connected Gate area |
20 |
Ant.d |
Max. ratio of cumulative via area (from Via1 to TopVia2) to connected Gate area (without protection diode) |
20 |
Ant.e |
Max. ratio of cumulative metal area (from Metal1 to TopMetal2) to connected Gate area (with protection diode) |
20000 |
Ant.f |
Max. ratio of cumulative via area (from Via1 to TopVia2) to connected Gate area (with protection diode) |
500 |
Ant.g |
Size of protection diode (um2) (Note 4) |
0.16 |
LU.b |
Max. space from any portion of N+Activ inside PWell to an pSD-PWell tie |
20 |
Slt.e1 |
No slits required on MIM |
|
Slt.i.M1 |
Min. Metal1:slit density for any Metal1 plate bigger than 35 um x 35 um [%] |
6 |
Slt.i.M2 |
Min. Metal2:slit density for any Metal2 plate bigger than 35 um x 35 um [%] |
6 |
Slt.i.M3 |
Min. Metal3:slit density for any Metal3 plate bigger than 35 um x 35 um [%] |
6 |
Slt.i.M4 |
Min. Metal4:slit density for any Metal4 plate bigger than 35 um x 35 um [%] |
6 |
Slt.i.M5 |
Min. Metal5:slit density for any Metal5 plate bigger than 35 um x 35 um [%] |
6 |
Slt.i.TM1 |
Min. TopMetal1:slit density for any TopMetal1 plate bigger than 35 um x 35 um [%] |
6 |
Slt.i.TM2 |
Min. TopMetal2:slit density for any TopMetal2 plate bigger than 35 um x 35 um [%] |
6 |
Pin.a |
Min. Activ enclosure of Activ:pin |
0 |
Pin.b |
Min. GatPoly enclosure of GatPoly:pin |
0 |
Pin.e |
Min. Metal1 enclosure of Metal1:pin |
0 |
Pin.f_M2 |
Pin.f Min. Metal2 enclosure of Metal2:pin |
0 |
Pin.f_M3 |
Pin.f Min. Metal3 enclosure of Metal3:pin |
0 |
Pin.f_M4 |
Pin.f Min. Metal4 enclosure of Metal4:pin |
0 |
Pin.f_M5 |
Pin.f Min. Metal5 enclosure of Metal5:pin |
0 |
Pin.g |
Min. TopMetal1 enclosure of TopMetal1:pin |
0 |
Pin.h |
Min. TopMetal2 enclosure of TopMetal2:pin |
0 |
LBE.a |
Min. LBE width |
100 |
LBE.b |
Max. LBE width |
1500 |
LBE.b1 |
Max. LBE area (µm²) |
250000 |
LBE.c |
Min. LBE space or notch |
100 |
LBE.d |
Min. LBE space to inner edge of EdgeSeal |
150 |
LBE.h |
No LBE ring allowed |
|
LBE.i |
Max. global LBE density [%] |
20 |
forbidden.BiWind |
BiWind is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.PEmWind |
PEmWind is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.BasPoly |
BasPoly is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.DeepCo |
DeepCo is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.PEmPoly |
PEmPoly is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.EmPoly |
EmPoly is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.LDMOS |
LDMOS is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.PBiWind |
PBiWind is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.NoDRC |
NoDRC is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.Flash |
Flash is forbidden in designs submitted for all 0.13 µm technologies. |
|
forbidden.ColWind |
ColWind is forbidden in designs submitted for all 0.13 µm technologies. |