IHP 130nm BiCMOS Open Source PDK
PDK Contents
Installation
Process Specifications
Layout Rules
Analog Design
Digital Design
Chip Finishing
Physical & Design Verification
Design Rule Checking (DRC)
Layout Versus Schematic (LVS) Checking
1. General
2. Layers
3. Truth Table for SG13G2 SiGe BiCMOS Process
4. Devices
5. Klayout-LVS
6. Magic-LVS
Parasitic Extraction (PEX)
EM Simulation
Contribution
References
IHP 130nm BiCMOS Open Source PDK
Physical & Design Verification
LVS Devices
6.
Magic-LVS
View page source
6.
Magic-LVS
TODO: verification/lvs/magic