IHP 130nm BiCMOS Open Source PDK Logo
  • PDK Contents
  • Installation
  • Process Specifications
    • 1. General Information
    • 2. Process Control Parameters
    • 3. Bipolar Parameters
    • 4. Attachment A: Measurement Conditions
    • 5. Change History
    • 6. Known Issues
  • Layout Rules
  • Analog Design
  • Digital Design
  • Chip Finishing
  • Physical & Design Verification
  • EM Simulation
  • Contribution
  • References
IHP 130nm BiCMOS Open Source PDK
  • Process Specifications
  • View page source

Process Specifications

IHP Open Source PDK

130nm BiCMOS Technology

IHP-SG13G2

Process Specifications

Rev. 1.2

Contents

  • 1. General Information
    • 1.1. Main Processing Sequence and Cross-Section Schematic
    • 1.2. Process Control
      • 1.2.1. Pass/Fail Parameters
      • 1.2.2. Information Parameters
    • 1.3. Wafer Reject Criteria
  • 2. Process Control Parameters
    • 2.1. NMOS-Specs
    • 2.2. PMOS-Specs
    • 2.3. iNMOS-Specs
    • 2.4. HV-NMOS-Specs
    • 2.5. HV-PMOS-Specs
    • 2.6. HV-iNMOS-Specs
    • 2.7. Rsil-Specs
    • 2.8. Rppd-Specs
    • 2.9. Rhigh-Specs
    • 2.10. Schottky_nbl1-Specs
    • 2.11. S-Varicap-Specs
    • 2.12. MIM Capacitor-Specs
    • 2.13. Resistances, Line Width Deltas, Temperature Coefficients
    • 2.14. Contact & Via Resistances
    • 2.15. Maximum Current Densities
    • 2.16. Layer Thickness Values
    • 2.17. Parasitic Capacitances
  • 3. Bipolar Parameters
    • 3.1. npn13g2-Specs
    • 3.2. npn13g2l-Specs
    • 3.3. npn13g2v-Specs
  • 4. Attachment A: Measurement Conditions
  • 5. Change History
  • 6. Known Issues
Previous Next

© Copyright 2024, IHP PDK Authors.

Built with Sphinx using a theme provided by Read the Docs.