IHP 130nm BiCMOS Open Source PDK
PDK Contents
Installation
Process Specifications
Layout Rules
Analog Design
Digital Design
Chip Finishing
Physical & Design Verification
Design Rule Checking (DRC)
Layout Versus Schematic (LVS) Checking
1. General
2. Layers
3. Truth Table for SG13G2 SiGe BiCMOS Process
4. Devices
5. Klayout-LVS
6. Magic-LVS
Parasitic Extraction (PEX)
EM Simulation
Contribution
References
IHP 130nm BiCMOS Open Source PDK
Physical & Design Verification
LVS Devices
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LVS Devices
IHP Open Source PDK
130nm BiCMOS Technology
IHP-SG13G2
LVS Devices
Contents
1. General
1.1. Purpose
1.2. Abbreviations
1.3. Derived Layers
1.4. Glossary of Terms
2. Layers
2.1. Layers Definition
2.2. Layout Layers
3. Truth Table for SG13G2 SiGe BiCMOS Process
4. Devices
4.1. MOSFET Devices
4.1.1. nmos
4.1.2. nmosHV
4.1.3. pmos
4.1.4. pmosHV
4.2. RFMOSFET Devices
4.2.1. rfnmos
4.2.2. rfnmosHV
4.2.3. rfpmos
4.2.4. rfpmosHV
4.3. BJT Devices
4.3.1. npn13G2
4.3.2. npn13G2L
4.3.3. npn13G2V
4.3.4. pnpMPA
4.4. Diode Devices
4.4.1. dantenna
4.4.2. dpantenna
4.4.3. schottky_nbl1
4.5. Resistor Devices
4.5.1. rhigh
4.5.2. rppd
4.5.3. rsil
4.5.4. lvsres
4.6. Capacitor Devices
4.6.1. cmim
4.6.2. rfcmim
4.6.3. SVaricap
4.7. ESD Devices
4.7.1. diodevdd_2k
4.7.2. diodevdd_4k
4.7.3. diodevss_2k
4.7.4. diodevss_4k
4.7.5. idiodevdd_2k
4.7.6. idiodevdd_4k
4.7.7. idiodevss_2k
4.7.8. idiodevss_4k
4.7.9. nmoscl_2
4.7.10. nmoscl_4
4.7.11. scr1
4.8. Inductor Devices
4.8.1. inductor
4.8.2. inductor3
4.9. Tap Devices
4.9.1. ptap1
4.9.2. ntap1
5. Klayout-LVS
5.1. Folder Structure
5.2. Prerequisites
5.3. Installation
5.4. Usage
5.4.1. CLI
5.4.2. GUI
5.5. LVS Testing
5.5.1. Folder Structure
5.5.2. Devices Status
5.5.3. Devices Regression Usage
5.5.4. Cells Regression Usage
5.5.4.1. LVS Outputs
6. Magic-LVS